Non-volatile phase-change memory cells are desirable elements of integrated circuits due to their ability to maintain data absent a supply of power. Various variable resistance materials have been investigated for use in non-volatile memory cells, including chalcogenide alloys, which are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state and the resistance states can be used to distinguish the logic values of the memory cell. Specifically, an amorphous state exhibits a relatively high resistance, while a crystalline state exhibits a relatively low resistance.
One such phase-change memory cell 110 may have the structure illustrated in FIGS. 1A and 1B, which includes a layer of phase-change material 116 between first and second electrodes 112, 118, which are supported by a dielectric material 114 that has an opening containing the first electrode 112. The phase-change material 116 is set to a particular resistance state according to the amount of current applied by the first and second electrodes 112, 118. To obtain an amorphous state (FIG. 1B), an initial write current pulse (i.e., a reset pulse) is applied for a first period of time through the conventional phase-change memory cell 110 to alter at least a portion 126 of the phase-change material 116 adjacent to the first electrode 112. The current is removed and the phase-change material 116 cools to a temperature below the crystallization temperature, which results in the portion 126 of the phase-change material 116 covering the first electrode 112 having the amorphous state. To obtain a crystalline state (FIG. 1A), a write current pulse (i.e., a set pulse) lower than the initial write current pulse is applied to the phase-change memory cell 110 for a second period of time, which is typically longer in duration than the crystallization time of amorphous phase-change material, resulting in the heating of the amorphous portion 126 of the phase-change material 116 to a temperature below its melting point, but above its crystallization temperature. This causes the amorphous portion 126 of the phase-change material 116 to re-crystallize. The amorphous portion 126 recrystallizes to a state that is maintained once the current is removed and the phase-change memory cell 110 is cooled. The phase-change memory cell 110 is read by applying a read voltage to the electrodes 112, 118, which does not change the state of the phase-change material 116, but which permits reading of the resistance of the phase-change material 116.
One potential drawback of the above described phase-change memory device 110 is the large programming current needed to achieve the phase change. This need for the large current is a limitation when attempting to reduce the size of the memory cell and when large memory cell arrays are fabricated. Another problem associated with the above described phase-change memory cell 110 is heat loss. Since the phase-change material 116 is in direct contact with a large area of the first electrode 112, there may be a significant amount of heat loss resulting in a large reset current requirement. Additionally, since the programmable volume (i.e., portion 126) of the phase-change material 116 is not confined and has the freedom to extend sideways during phase change, switching stability may be reduced.
One technique to reduce the high current requirement, reduce heat loss, and improve switching stability confines and reduces the programmable volume of the phase-change material 116 and also reduces the electrode area in contact with the programmable volume. FIG. 2A illustrates one example of a phase-change memory cell 210 using the confined technique. To fabricate the phase-change memory cell 210, a via, e.g. a cylindrical via, is etched into a second insulating layer 224 to expose the first electrode 212. A layer of phase-change material 216 is deposited along the sidewall 230 of the via 222 to serve as the programmable volume of the phase-change memory cell 210. A third insulating layer 228 is deposited over the phase-change material 216 and within the via 222. A subsequent chemical-mechanical planarization (CMP) step removes the phase-change material 216 and the insulating material 228, stopping at the second insulating layer 224. The CMP process exposes a ring 232 of phase-change material 216, which can be covered by and in contact with the second electrode 218.
Referring to FIG. 2B, it is known that due to arrival angle distribution and poor step coverage, a conventional physical vapor deposition (PVD) process cannot always accurately control the thickness of the phase-change material 216 deposited along the sidewall 230 of a via 222. The thick layer of phase-change material deposited on a field region 231 surrounding the via 222 poses a problem for the subsequent CMP process, as it introduces large film stress and phase-change material adhesion issues during the CMP process. An excessive overhang of material at the top of the via 222 may cause a “necking in” of the opening which may restrict or prohibit subsequent thin film depositions and/or filling of the structure. This problem may result in voids in the phase-change memory cell and failed memory devices.
It is therefore desirable to use a fabrication process that provides the level of anisotropy needed at the interface between heater and phase-change material without introducing problems in the overall process flow. It is also desirable to reduce voids and provide a method of fabricating a semiconductor device that allows for the recovery of failed devices due to an excessive overhang of material at the opening of phase-change memory vias.